july 2000 ML2330 * selectable dual 3v/3.3v/5v 8-bit dacs features 3v 10%, 3.3 10% or 5v 10% operation low supply current (3.5ma max) individual and full power down (down to 1 a) 10mb/s three-wire serial interface, compatible to spi and microwire 8-pin soic package available in extended commercial temperature range (C20 c to 70 c) and industrial temperture range (C40 c to 85 c) guaranteed monotonicity general description the ML2330 selectable dual 3v/3.3v/5v 8-bit dacs are dual voltage output digital-to-analog converters which can be independently programmed, or powered down to conserve power. the devices are intended for use in portable or low power 3v systems where space is critical. programming access to the dacs is provided over a high speed (10mb/s), 3-wire serial interface which is compatible to the spi? and microwire? data formats. in addition to independent programming of the dac output voltages, each device may be powered down, independent of the other dac, to conserve power. each dac draws 2ma maximum quiescent current when operating, and typically less than 1 a when powered down. the device comes in an 8-pin soic package and in a special extended commercial temperature range (C20 c to 70 c) or industrial temperture range (C40 c to 85 c). block diagram dac a r e g control and timing vref dac b r e g s clk d in cs d out out b out a gnd vcc power down 20k ? 20k ? 3 1 2 8 7 6 5 4 *some packages are end of life or obsolete rev. 1.0 10/10/2000
ML2330 2 rev. 1.0 10/10/2000 pin configuration pin description pin name function 1d in data in 2s clk serial clock 3 cs chip select 4d out data out 5 gnd ground 6 out b output of dac b 7 out a output of dac a 8v cc positive supply ML2330 8-pin soic (s08) v cc out a out b gnd 1 2 3 4 8 7 6 5 d in s clk cs d out top view
ML2330 rev. 1.0 10/10/2000 3 absolute maximum ratings supply voltage (v cc ) ................................................ 6.0v gnd ................................................ C0.3v to v cc + 0.3v logic inputs ..................................... C0.3v to v cc + 0.3v input current per pin ............................................ 25ma storage temperature ................................ C65 c to 150 c package dissipation at t a = 25 c ....................... 750mw lead temperature (soldering 10 sec.) soic ..................................................................... 150 c operating conditions supply voltage (v cc ) ML2330esC2 ................................................ 3v 10% ML2330esC3 ............................................. 3.3v 10% ML2330esC5 ................................................ 5v 10% temperature range ML2330es ............................................. C20 c to 70 c ML2330is .............................................. C40 c to 85 c electrical characteristics unless otherwise specified, t a = t min to t max , v cc = operating supply voltage range, f clk = 10mhz r l = 1k ? , (r l = 2k ? for v cc = 5v), c l = 100pf (note 1) parameter symbol conditions min typ max units converter resolution 8 bits integral linearity error ile 1.5 lsb differential linearity error dle 1lsb offset error v cc = 3.3v or 3.0v e suffix 10 20 30 mv i suffix 5 20 35 mv v cc = 5v e suffix 15 25 35 mv i suffix 10 25 40 mv gain error 5 %fs analog output output drive current i outpp full scale output 2 ma power supply rejection ratio psrr @00 & ff 40 db digital and dc logic input low v il v cc = 3v, 3.3v, or 5v 0.8 v logic input high v ih v cc = 3v or 3.3v 2.0 v v cc = 5v 2.8 v logic input low current i il v in = gnd C1 a logic input high current i ih v in = v cc 1 a logic output low v ol i = 3.2ma 0.4 v logic output high v oh i = 0.4ma 2.4 v supply current i cc r l = 2.5 3.5 ma power down current all digital inputs at v cc = 3v 3 a static 0v or v cc v cc = 5v 5 a ac performance settling time t s 1/2 lsb 5 10 s slew rate 1.4 v/ s crosstalk 60 db note 1: limits are guaratneed by 100% testing, sampling or correlation with worst case test conditions.
ML2330 4 rev. 1.0 10/10/2000 timing characteristics (serial interface) v cc = operating supply voltage range, c l = 50pf, t a = t min to t max , unless otherwise noted parameter symbol conditions min typ max units converter cs fall to s clk setup time t css 20 ns s clk rise to cs rise hold time t csh 50 ns d in to s clk rise setup time t ds 20 ns d in to s clk rise hold time t dh 20 ns s clk frequency f clk 10 mhz s clk duty cycle 40 60 % s clk to d out valid t do v cc = 3.3v or 5v 30 60 ns v cc = 3v 45 90 ns figure 1c. interface timing cs s clk d in d out * *d out is the data from previous input. a1 a0 p1 p0 d7 d6 d5 d4 d3 d2 d1 d0 d0 a1 a0 p1 p0 d7 d6 d5 d4 d3 d2 d1 d0 figure 1a. connections for microwire. figure 1b. connections for spi. s clk d in d out cs sk so si i/o ML2330 microwire port 2 1 4 3 d out s clk d in cs miso mosi sck i/o ML2330 spi port 4 1 2 3
ML2330 rev. 1.0 10/10/2000 5 the 4-bit address/control code configures the dac as shown in table 1. a1 a0 function 0 0 no operation 0 1 select control bits and dac a 1 0 select control bits and dac b 1 1 select control bits and both dacs table 1.1 address selection p1 p0 function 0 0 normal 0 1 power down dac a 1 0 power down dac b 1 1 power down entire chip table 1.2 power down selection dac operation the dacs are implemented using an array of equal current sources that are decoded linearly for the four most significant bits to improve differential linearity and to reduce output glitch around major carries. a voltage difference between on-board bandgap reference voltage and gnd is converted to a reference current using an internal resistor to set up the appropriate current level in the dacs. the dacs output current is then converted to a voltage output by an output buffer and a resistive network. the matching among the on-chip resistors preserves the gain accuracy between these conversions. functional description serial interface the ML2330 communicates with microprocessors through a synchronous, full-duplex, 3-wire interface (figure 1a & b). at power on, the control registers are cleared and both dacs have high impedance outputs. data timing shown in figure 1c is sent msb-first and can be transmitted in one 4-bit and one 8-bit packet or in one 12-bit word. if a 16-bit control word is used, the first four bits are ignored. the serial clock (s clk ) synchronizes the data transfer. data is transmitted and received simultaneously. figure 2 shows detailed serial interface timing. note that the clock should be low between updates. d out does not go into a high impedance state if the clock idles or cs is high. serial data is clocked into the data registers in msb-first format, with the address and configuration information preceding the actual dac data. data is sampled on the s clk s rising edge while cs is low. data at d out is clocked out 12.5 clock cycles later, on the s clk s falling edge. chip select ( cs ) must be low to enable the read or write operation. if cs is high, the interface is disabled and d out remains unchanged. cs must go low at least 10ns before the first clock pulse to properly clock in the first bit. with cs low, data is clocked into the ML2330s internal shift register on the rising edge of the external serial clock. s clk can be driven at rates up to 10mhz. serial input data format and configuration codes the 12-bit serial input format shown in figure 3 comprises two dac address bits (a1, a0), two power down control bits (p1, p0) and eight bits of data (d7 . . . d0). dout a1 a0 p1 d7 . . . d0 din figure 3. serial input format figure 2. detail interface timing cs s clk d in d out t css t ds t dh t do t csh
ML2330 6 rev. 1.0 10/10/2000 voltage reference a bandgap voltage reference is incorporated on the ML2330. it is trimmed for zero temperature coefficient at 25 c to minimize output voltage drift over the specified operating temperature range. output buffer and gain setting the output buffer converts the dac output current to a voltage output using a resistive network. the outputs can swing from gnd +0.02v to either 2.02v (3v) or 4.02v (5v). the dac transfer function is: v kdata out = + 256 002 . where k = 2 if v cc = 3v and k = 4 if v cc = 5v in the 3v operation, the amplifier outputs will settle to 1/2lsb in 10 s when loads are greater than 1k ? (2k ? for 5v operation) and capacitive loads smaller than 100pf. gain error the graph below shows how gain error varies with temperature when v cc = 3.3v. power down mode there are three power-down modes in the ML2330. by clearing the control bits p1-p0 (table 3.2), the entire chip will be powered down with a supply current less than 5 a. individual dacs can also be powered down to save power (1.75ma per dac). ?40 ?20 0 20 40 60 80 100 temperature ( c) 0.4 0.3 0.2 0.1 ?0.0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 ?0.7 ?0.8 ?0.9 ?1.0 gain error (%) gain error vs temperature
ML2330 rev. 1.0 10/10/2000 7 part number v cc temperature range package ML2330esC2 3v C20 c to 70 c 8-pin soic (s08) ML2330esC3 (end of life) 3.3v C20 c to 70 c 8-pin soic (s08) ML2330esC5 (end of life) 5v C20 c to 70 c 8-pin soic (s08) ML2330isC2 3v C40 c to 85 c 8-pin soic (s08) ML2330isC3 (obsolete) 3.3v C40 c to 85 c 8-pin soic (s08) ML2330isC5 5v C40 c to 85 c 8-pin soic (s08) physical dimensions inches (millimeters) seating plane 0.148 - 0.158 (3.76 - 4.01) pin 1 id 0.228 - 0.244 (5.79 - 6.20) 0.189 - 0.199 (4.80 - 5.06) 0.012 - 0.020 (0.30 - 0.51) 0.050 bsc (1.27 bsc) 0.015 - 0.035 (0.38 - 0.89) 0.059 - 0.069 (1.49 - 1.75) 0.004 - 0.010 (0.10 - 0.26) 0.055 - 0.061 (1.40 - 1.55) 8 0.006 - 0.010 (0.15 - 0.26) 0 o - 8 o 1 0.017 - 0.027 (0.43 - 0.69) (4 places) package: s08 8-pin soic ordering information life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com ?2000 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
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